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AL440B Data Sheets Version 1.4 AVERLOGIC TECHNOLOGIES, CORP. TEL: 886 227915050 e-mail: sales@averlogic.com.tw URL: www.averlogic.com.tw AVERLOGIC TECHNOLOGIES, INC. TEL: 1 408 361-0400 e-mail: sales@averlogic.com URL: www.averlogic.com February 21, 2003 AL440B Amendments 11-28-01 03-11-02 05-14-02 11-11-02 12-30-02 02-20-03 AL440B version 1.0 release data sheets. Version 1.1, remove cascade information Version 1.2, revised I2C diagram Version 1.3, Revised Electronically Characteristic with 5V signals input tolerance Version 1.4, Revised "TEST" and "/PLTY" pin description Company Contact Information updated AL440B February 20, 2003 2 AL440B AL440B 4MBits FIFO Field Memory Contents: 1.0 Description _________________________________________________________________ 4 2.0 Features____________________________________________________________________ 4 3.0 Applications_________________________________________________________________ 4 4.0 Ordering Information _________________________________________________________ 4 5.0 Pin-out Diagram _____________________________________________________________ 5 6.0 Block Diagram ______________________________________________________________ 5 7.0 Pin Definition and Description _________________________________________________ 6 8.0 Register Definition ___________________________________________________________ 8 8.1 Register Set ____________________________________________________________________________ 8 9.0 Multiple Devices Bus Expansion ________________________________________________ 9 10.0 Serial Bus Interface _________________________________________________________ 9 11.0 Memory Operation _________________________________________________________ 11 11.1 Power-On-Reset & Initialization __________________________________________________________ 11 11.2 WRST, RRST Reset Operation ___________________________________________________________ 11 11.3 Control Signals Polarity Select ___________________________________________________________ 11 11.4 FIFO Write Operation __________________________________________________________________ 12 11.5 FIFO Read Operation___________________________________________________________________ 12 11.6 IRDY, ORDY Flags____________________________________________________________________ 13 11.7 Window Write Register Programming _____________________________________________________ 14 11.8 Window Read Register Programming ______________________________________________________ 17 12.0 Electrical Characteristics ____________________________________________________ 20 12.1 Absolute Maximum Ratings _____________________________________________________________ 20 12.2 Recommended Operating Conditions ______________________________________________________ 20 12.3 DC Characteristics _____________________________________________________________________ 20 12.4 AC Characteristics _____________________________________________________________________ 21 13.0 Timing Diagrams __________________________________________________________ 23 14.0 Mechanical Drawing - 44 PIN PLASTIC TSOP (II) ______________________________ 31 15.0 Application Notes __________________________________________________________ 33 15.1 Chip Global Reset Recommend Circuit_____________________________________________________ 33 15.2 The AL440B Reference Schematic ________________________________________________________ 33 AL440B February 20, 2003 3 AL440B 1.0 Description The AL440B 4Mbits (512k x 8-bit) FIFO memory provides completely independent 8bit input and output ports that can operate at a maximum speed of 80 MHz. The built-in address and pointer control circuits provide a very easy-to-use memory interface that greatly reduces design time and effort. Manufactured using state-of-the-art embedded high density memory cell array, the AL440B uses high performance process technologies with extended controller functions (write mask, read skip.. etc.), allowing easy operation of non-linearity and regional read/write FIFO for PIP, Digital TV, security system and video camera applications. The status flags can be used to indicate Fullness/Emptiness of the FIFO. Expanding AL440B data bus width is possible by using multiple AL440B chips in parallel. To get better design flexibility, the polarities of the AL440B control signals are selectable. The read and write control signals, such as Read/Write Enable, Input/Output Enable.., can be either active low or high by pulling /PLRTY signal to high or low respectively. In AL440B, Window data write/read and data mirroring functions can offer better control assistance in the application design. The built-in registers set can be easily programmed via serial bus (I2C like control bus) to perform various useful functions such as multi-freeze, P-in-P in the digital TV, VCR, and video camera application. Available as a 44-pin TSOP (II), the small footprint allows product designers to keep real estate to a minimum. 2.0 Features * * * * * * * * * * * 4Mbits (512k x 8 bits) organization FIFO Independent 8bit read/write port operations (different read/write data rates acceptable) Maximum Read/write cycle time: 80Mhz and 40Mhz (2 speed grades) Input Enable (write mask) / Output Enable (data skipping) control Window read/write with Mirroring capable Selectable control signal polarity Input Ready / Output Ready flags Self refresh 5V signals input tolerance 3.3V 10% power supply Standard 44-pin TSOP (II) package 3.0 Applications * * * * * * * * * * Multimedia systems Video capture or editing systems for NTSC/PAL or SVGA resolution Security systems Scan rate converters PIP (Picture-In-Picture) video display TBC (Time Base Correction) Frame synchronizer Digital video camera Hard disk cache memory Buffer for communication systems * 80MHz High-Speed version * DTV/HDTV video stream buffer 4.0 Ordering Information The AL440B has two speed grades, AL440B-24 and AL440B-12, which can operate at frequencies of 40MHz and 80MHz respectively. Both speed grades are powered by 3.3V and are available in a 44-pin standard TSOP-II package. AL440B February 20, 2003 4 AL440B Part number AL440B-24 (40MHz) AL440B-12 (80MHz) Package 44-pin plastic TSOP(II) 44-pin plastic TSOP(II) Power Supply +3.3V10% +3.3V10% Status Sample Dec., 2001 Sample Dec.., 2001 5.0 Pin-out Diagram The AL440B pin-out diagram is following. SCL 24 21 44 43 42 41 40 39 38 37 36 35 OE 34 33 32 31 30 29 28 27 26 25 AVERLOGIC AL440B-XX XXXXX XXXX 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 Speed Lot Number Date Code 19 20 AVDD WE WCK DI0 DI1 DI2 DI3 DI4 DI5 DI6 DI7 GND TEST WRST /PLRTY AL440B-12/24 TSOP (II) pinout diagram (Top view) 6.0 Block Diagram DI[7:0] Input Buffer Write Data Register Internal Bus 512kx8 memory cell array Internal Bus Read Data Register AGND VDD IRDY IE NC NC NC /SDAEN 23 22 GND /RESET ORDY RRST GND RCK VDD VDD NC SDA DO0 DO1 DO2 DO3 DO4 DO5 DO6 DO7 RE Output Buffer DO[7:0] IRDY WCK WRST IE WE /SDAEN SCL & SDA Control Registers Iutput Control Memory Control Output Control Timing Generator & Arbiter Address Bus Control Bus ORDY RCK RRST OE RE To all Modules Refresh Counter To all Modules Timing & Logic Control /PLRTY /RESET AL440B Block Diagram AL440B February 20, 2003 5 AL440B The internal structure of the AL440B consists of an Input/Output buffers, Write Data Registers, Read Data Registers and main 512k x8 memory cell array and the state-of-the-art logic design that takes care of addressing and controlling the read/write data. 7.0 Pin Definition and Description The pin definitions and descriptions are as follows: Write Bus Signals Pin name Pin number I/O type Description DI[7:0] 9,8,7,6,4,3,2, 1 10 11 I WE IE I I WCK WRST IRDY 13 14 15 I I O The DI pins input 8bits of data. Data input is synchronized with the WCK clock. Data is acquired at the rising edge of WCK clock. WE is an input signal that controls the 8bit input data write and write pointer operation. IE is an input signal that controls the enabling/ disabling of the 8bit data input pins. The internal write address pointer is always incremented at rising edge of WCK by enabling WE regardless of the IE level. WCK is the write clock input pin. The write data input is synchronized with this clock. The WRST is a reset input signal that resets the write address pointer to 0. IRDY is a status output flag that reports the FIFO space availability. *Note: For the polarity definition of all write control signals (WE, IE, WRST and IRDY), please refer to /PLRTY pin definition and "Memory Operation" section for details. Read Bus Signals Pin name DO[7:0] Pin number I/O Description type 36,37,38,39, O The DO pins output 8bit of data. Data output is 41,42,43,44 synchronized with the RCK clock. Data is output at the rising edge of the RCK clock. 35 I RE is an input signal that controls the 8bit output data read and read pointer operation. 34 I OE is an input signal that controls the enabling/ disabling of the 8bit data output pins. The internal read address pointer is always incremented at rising edge of RCK by enabling RE regardless of the OE level. 32 I RCK is the read clock input pin. The read data RE OE RCK AL440B February 20, 2003 6 AL440B RRST ORDY 31 30 I O output is synchronized with this clock. The RRST is a reset input signal that resets the read address pointer to 0. ORDY is a status output flag that reports the FIFO data availability. *Note: For the polarity definition of all read control signals (RE, OE, RRST and ORDY), please refer to /PLRTY pin definition and "Memory Operation" section for details. Serial Port Bus Signals Pin name SDA Description Pin number I/O type 25 I/O SDA carries the serial bus read/write data bits. The SDA data bit is valid when the SCL is high after start up sequence. 24 I SCL supplies the serial bus clock signal to FIFO. The serial data bit is valid when the SCL is high after start up sequence. 23 I /SDAEN controls the enabling/disabling of serial bus interface. When /SDAEN is high, the serial interface is disabled and SDA pin is high impedance. When /SDAEN is low, the serial interface is enabled and data can be written to or read from the FIFO registers. SCL /SDAEN Power/Ground Signals Pin name VDD GND AVDD AGND Description Pin number I/O type 5, 29, 40 - 3.3V 10%. 12, 26, 33 - Ground. 18 - Dedicated power pin for the internal oscillator. 3.3V 10%. 22 - Dedicated ground pin for the internal oscillator. Miscellaneous Signals Pin name /RESET Pin number I/O Description type 27 I The global reset pin /RESET will automatically initialize chip logic. For the recommended circuit for the global reset signal, please refer to the Application Notes. AL440B February 20, 2003 7 AL440B /PLRTY 16 I TEST NC 17 19,20,21,28 I - Select active polarity of the control signals including WE, RE, WRST, RRST, IE, OE, IRDY and ORDY totally 8 signals /PLRTY = VDD, active low. /PLRTY = GND, active high. Note: During memory operation, the pin must be permanently connected to VDD or GND. The pin has internal Pull-High as default active low, if /PLRTY has no connection. If /PLRTY level is changed during memory operation, memory data is not guaranteed. For testing purpose only. Connect to Ground. No connect or connect to Ground 8.0 Register Definition There are some built-in registers in the AL440B that allows performing some optional functions such as window read/write access. These registers can be programmed via serial bus (SDA, SCL and /SDAEN). The serial bus interface protocol is illustrated in "Serial Bus Interface" chapter. The serial bus control software code or tool is available at Averlogic Technologies, Inc. upon request. 8.1 Register Set Address 00h 02h 03h 04h 05h 06h 07h 08h 09h 0Ah Register COMPANYID WSTART_L WSTART_H WXSIZE_L WXSIZE_H WSTRIDE_L WSTRIDE_H WYSIZE_L WYSIZE_H WWCTRL R/W R R/W R/W R/W R/W R/W R/W R/W R/W R/W Description Company ID (46h) Window write starting address (Low byte) Window write starting address (High byte) Window write horizontal size (Low byte) Window write horizontal size (High byte) Window write strike size (Low byte) 2's complement (for Y-mirror) Window write strike size (High byte) 2's complement (for Y-mirror) Window write vertical size (Low byte) Window write vertical size (High byte) Window write control register [7]: enable window write function [6]: X mirror [5]: freeze Window read starting address (Low byte) Window read starting address (High byte) Window read horizontal size (Low byte) Window read horizontal size (High byte) Window read strike size (Low byte) Window read strike size (High byte) 8 0Bh 0Ch 0Dh 0Eh 0Fh 10h RSTART_L RSTART_H RXSIZE_L RXSIZE_H RSTRIDE_L RSTRIDE_H R/W R/W R/W R/W R/W R/W AL440B February 20, 2003 AL440B 11h 12h 13h RYSIZE_L RYSIZE_H RWCTRL R/W Window read vertical size (Low byte) R/W Window read vertical size (High byte) R/W Window read control register [7]: enable window read function 9.0 Multiple Devices Bus Expansion The AL440B FIFO memory can be applied to very wide range of media applications. A parallel connect of multiple AL440B FIFOs provides FIFO bus width. WRST DI[7:0] IE IRDY WE WCK RRST DO[7:0] OE ORDY RE RCK 16-bit Input Bus Width 16-bit Output Bus Width WRST DI[7:0] IE IRDY WE WCK RRST DO[7:0] OE ORDY RE RCK AL440B Data Bus Width Expansion 10.0 Serial Bus Interface The serial bus interface consists of the SCL (serial clock), SDA (serial data) and /SDAEN (serial interface enable) signals. There are pulling up circuit internally for both SCL and SDA pins. When /SDAEN is high, the serial bus interface is disabled and both SCL and SDA pins are pulled high. When /SDAEN is low, the serial bus interface is enabled and data can be written into or read from the AL440B register set. For both read and write, each byte is transferred MSB first and LSB last, and the SDA data bit is valid when the SCL is pulled high. The serial bus control sample C code is available in Averlogic Technologies, Inc. upon request. The read/write command format is as follows: AL440B February 20, 2003 9 AL440B Write: |
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